Evolutionary Design of Hashing Function Circuits Using an FPGA
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چکیده
An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16 bit address space into an 8 bit one. This circuit, based on FPGAs, is readily applicable to the design of set-associative cache memories. Possible use the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.
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تاریخ انتشار 1998